1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to reading-related circuitry in a semiconductor memory device.
2.Description of the Background Art
In recent years, as the storage capacity of semiconductor integrated circuit devices has increased, the critical dimension (the minimum manufacturable size) of transistors which form memory cells in the devices has been reduced as well. This gives rise to the necessity of miniaturizing transistors which form peripheral circuits and interconnections as well as the necessity of miniaturizing those which form memory cells.
The miniaturization of transistors to form sense amplifiers used for sensing slight potential difference generated between a bit line pair at the time of reading out data from a memory cell means a decline in the current driving capability per transistor. Thus, time required for the sense amplifier circuit to drive input/output (hereinafter "I/O") line pairs in the array to indirect peripheral circuits such as an I/O line pair to a main amplifier increases.
A so-called direct-sense scheme is known as a method for solving such a disadvantage. An example of the direct-sense scheme is shown in FIG. 30.
The gates of transistors 902 and 904 receive the potential levels of data line pairs DL1 and /DL1, respectively, the potential difference of which is amplified by a sense amplifier 900 according to the storage information of a selected memory cell.
The sources of transistors 902 and 904 are supplied with a ground potential through a transistor 906 having its gate potential controlled by read control signal iore.
Transistor 902 has its drain connected to a data line DL2 through a transistor 908 having its gate potential controlled by a reading control signal iore. Meanwhile, transistor 904 has its drain connected to a data line /DL2 through a transistor 910 having its gate potential controlled by reading control signal iore.
Data read out from a memory cell is transmitted to an indirect peripheral circuit 920 by data line pair DL2, /DL2.
Hereinafter, the circuit formed by transistors 902 to 910 will be called "a sub-amplifier".
In such direct sense scheme, data line pair DL1, /DL1 and data line pair DL2, /DL2 are isolated by transistors 902 and 904. As a result, the capacity driven by sense amplifier 900 is simply that of data line pair DL1, /DL1 to transistors 902 and 904, while data line pair DL2, /DL2 are driven by the sub-amplifier.
More specifically, the capacity driven by sense amplifier 900 is restrained, which allows for accessing at a higher speed.
However, in order to further increase the accessing speed, the following problem will be encountered.
In the conventional configuration shown in FIG. 30, a sense amplifier itself is often provided at the position of the sub-amplifier described above.
Alternatively, such a sub-amplifier is often located at a crossing point of a sense amplifier band and a sub-word driver band (hereinafter referred to as "a cross point").
FIG. 31 is a schematic block diagram of an example of such a configuration.
Referring to FIG. 31, there are provided a main row decoder 940 and a column decoder 950 corresponding to a memory mat 930.
Memory mat 930 is divided into sub-blocks 936 by sense amplifier bands 932 and word driver regions 934.
In this configuration, sub-amplifiers SUA are provided at cross points of local I/O line pairs in the row-direction and global I/O line pairs in the column direction.
Signal iore to control sub-amplifier SUA is generated by main row decoder 940 and transmitted in the row-direction to sub-amplifier SUA
However, the data reading operation itself is the operation by the column-related circuitry, and therefore, a signal line to transmit signal iore provided in the row-direction and a column selecting line YS to transmit a column selecting signal are perpendicular to each other. When column selecting line YS and the path to transmit signal iore are provided perpendicular to each other, a timing margin should be secured between the signals in view of skew between the signals, which impairs the accessing time from being reduced.
The miniaturization of a transistor forming sub-amplifier SUA increases sub-threshold leakage current by the transistor, and the power consumption disadvantageously increases by a constant amount of leakage current generated, even if the circuit is in a stand-by state, in other words, if transistor 906 is in a disconnected state.